THRESHOLD VOLTAGE DEGRADATION IN PLASMA-DAMAGED CMOS TRANSISTORS - ROLE OF ELECTRON AND HOLE TRAPS RELATED TO CHARGING DAMAGE

The paper presents results of study of threshold voltage (V-T) degrada tion in CMOS transistors damaged by high-field charging, Fowler-Nordhe im stress induced V-T degradation in devices with latent charging dama ge due to plasma processing was found to be strongly dependent on devi ce type and diagnostic stress conditions, ''Direct'' and ''reverse'' a ntenna effect for NMOS, and anomalous behavior of PMOS devices are exp lained with polarity dependent trapping and the model includes generat ion of hole traps, an effect not considered previously. Copyright (C) 1996 Elsevier Science Ltd