JUSTIFICATIONS FOR REDUCING HBM AND MM ESD QUALIFICATION TEST TIME

Authors
VERHAEGE K ROBINSONHAHN D RUSS C FARRIS M SCANLON J LIN D VELTRI J GROESENEKEN G
Citation
K. Verhaege et al., JUSTIFICATIONS FOR REDUCING HBM AND MM ESD QUALIFICATION TEST TIME, Microelectronics and reliability, 36(11-12), 1996, pp. 1715-1718
Citations number
7
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Microelectronics and reliability → ACNP
ISSN journal
00262714
Volume
36
Issue
11-12
Year of publication
1996
Pages
1715 - 1718
Database
ISI
SICI code
0026-2714(1996)36:11-12<1715:JFRHAM>2.0.ZU;2-1
Abstract
Reducing the HEM and MM qualification time has become a primary concer n of IC manufacturers. The reduction of pin combinations, and, the tim e interval between zaps (by a factor of 10 to ultimately 100) is justi fied. Copyright (C) 1996 Elsevier Science Ltd