FUNCTIONALLY ASYNCHRONOUS ARRAY PROCESSOR FOR MORPHOLOGICAL FILTERINGOF GREYSCALE IMAGES

The design of a fine-grain asynchronous VLSI array processor is presen ted. It demonstrates how asynchronism can be exploited both at functio nal and architectural levels. A joint algorithm-architecture study tha t has resulted in the design of a 16 x 16 processor array is described , and the design flow used to implement both data-paths and control pa rts is presented. This is based on a standard cell approach that combi nes differential cascode voltage switch logic blocks and standard CMOS gates. The chip has been fabricated using the CNET/SGS-Thomson 0.5 mu m CMOS triple metal layer technology, including 800 000 transistors i n an area of 8 x 9 mm(2). This allows real-time iterative morphologica l filtering of greyscale 256 x 256 pixels images at similar to 40 Hz f rame rate.