DESIGN AND IMPLEMENTATION OF A GAAS SYSTOLIC FLOATING-POINT PROCESSING ELEMENT

The design and layout of a prototype single precision systolic floatin g-point processing element (PE) is described. It is intended for use i n a class of systolic array processors which perform matrix computatio ns. Each PE is constructed from a digit-serial systolic ring of four p rogrammable cells and performs floating-point multiplication and accum ulation. A single PE has been fabricated in a 0.8 mu m gallium arsenid e E/D MESFET process and has a maximum clock speed of 300 MHz. The chi p can be configured into a 16 x 16 array to achieve a peak computation rate of 2.5 GFLOPS.