DELAYED PRECISE INVALIDATION - A SOFTWARE CACHE COHERENCE SCHEME

Software cache coherence schemes are very desirable in the design of s calable multiprocessors and massively parallel processors. The authors propose a software cache coherence scheme named 'delayed precise inva lidation' (DPI). DPI is based on compiler-time markings of references and a hardware local invalidation of stale data in parallel and select ively. With a small amount of additional hardware and a small set of c ache management instructions, this scheme provides more cacheability a nd allows invalidation of partial elements in an array, overcoming som e inefficiencies and deficiencies of previous software cache coherence schemes.