A STUDY ON CHANNEL DESIGN FOR 0.1 MU-M BURIED P-CHANNEL MOSFET

This paper investigates the channel design for buried p-channel MOSFET 's with an effective channel length of 0.1 mu m via simulations using the two-dimensional device simulator PISCES IIB. A new three-layer des ign is considered with the objective of obtaining low junction capacit ance while maintaining high current drive and suppressing punchthrough , The channel design consists of a p-type layer under the gate oxide, an n-type anti-punchthrough layer below the p-type layer followed by t he substrate with a doping concentration of 1e17/cm(3). By optimizing the doping structure, an attempt is made to investigate fundamental li mits of the buried channel design, In concurrence with published resul ts, it is shown that there is a maximum allowable thickness for the fi rst layer, while the thickness of the anti-punchthrough layer has a mi nimum value in order to effectively suppress punchthrough, The above c onstraints enable devices with good subthreshold characteristics (subt hreshold swing <90 mV/Dec) as well as high transconductance which is a matter of concern for ultra-thin buried layers. While simulation resu lts show that it is possible to fabricate buried p-channel MOSFET's wi th n-type polysilicon gate electrodes in the 0.1 mu m regime, it is al so evident that advanced doping and low temperature fabrication techno logies are needed that pro,ide control over doped layers of ultra-thin dimensions.