AREA-EFFICIENT SYSTOLIC INTERCONNECTION NETWORKS

Area efficient VLSI design of interconnection networks is an important problem in multiprocessor design. In the context of ULSI technology, the delay in signal propagation along wires will become a significant limitation in designing large, fast networks. This limitation is parti cularly applicable for high wire organisations typically used in inter connection networks. In the paper, it is shown that classical cross-ba r type interconnection networks, formed as systolic arrays, have bette r composite VLSI performance metrics than most popular interconnection networks that use high wire organisations even though systolic organi sations have the disadvantage of being larger in terms of silicon area . The authors outline a new, hybrid architecture for interconnection n etworks that trades speed advantages of systolic arrays with area adva ntages of high wire organisations. An implementation, in VLSI, of a bu tterfly network using the proposed approach is described, and it is sh own why this is useful in designing an area efficient interconnection network.