An analytical model is developed to estimate the effect of the scaling
of the buried oxide on the heat flow in SOI devices. The heat evacuat
ion is shown to follow the buried oxide thickness to the n-th power wi
th -0.5 > n > -1, and it strongly depends on device dimensions. Three
experimental independent evidences of reduced self-heating in GAA devi
ces are provided and analyzed in the light of an analytical model. The
advantage of the GAA structure is to replace the buried oxide below t
he channel by a back polysilicon gate that benefits for a much larger
thermal conductivity. To achieve the same result in SOI devices, the b
uried oxide thickness should be reduced down to twice the gate oxide t
hickness, which unfortunately would also lead to a dramatic increase o
f source and drain parasitic capacitances. In the GAA transistor, on t
he contrary, source and drain regions still lie on the thick buried ox
ide layer such that those parasitic elements keep a low value.