CMOS VLSI RELIABILITY TEST MODEL

This paper introduces a Fault Model capable of elucidating the sensiti vity to Early Fault (EF) rising nature in CMOS VLSI circuits. The Mode l is based on the general Percolation Theory applied to the CMOS techn ology. CMOS VLSI circuit in steady state is represented as a non condu ctive network spread out between power supply, ground and input/output terminals. According to the percolation theory, in such a network the re is a definite critical number of conductive defects that cause a pe rmanent current path creation. The percolation current through this pa th applies a heavy stress condition to the circuit elements, causing t heir degradation. Early Failures screening technique employing this mo del, show a strong correlation between rejected devices and EF rate an d the common nature of sensitivity to EOS and EF. This technique is pa ttern independent, cost and time efficient and does not expose tested devices to any stress conditions. It is recommended, both as an EF scr eening test and a process reliability monitor. Copyright (C) 1996 Else vier Science Ltd