IMPACT OF POLYSILICON EMITTER INTERFACIAL LAYER ENGINEERING ON THE 1 F NOISE OF BIPOLAR-TRANSISTORS/

To optimize the electrical characteristics of polysilicon emitter bipo lar transistors, the poly emitter interface needs careful engineering, In this paper, bipolar transistors of a 0.5 mu m BiCMOS process have been fabricated with intentionally grown oxides in an LPCVD cluster fo r precise control over the interfacial oxide thickness and uniformity, The trade off between current gain enhancement and increased 1/f nois e will be discussed for various interfacial oxide thicknesses and emit ter annealing conditions, It will be demonstrated that for sufficientl y large base currents, both for large (20 mu m x 20 mu m) and small (0 .5 mu m x 5 mu m) emitter areas the interfacial oxide dominates the 1/ f noise spectrum of the base current, Hence, the polysilicon emitter i nterface engineering will not only set the current gain at a predefine d value, but at the same time the associated oxide-tunnelling noise is fixed, within the constraint that the emitter-base junction depth is constant, Finally, it will be shown that the current gain enhancement and increased 1/f noise have compensating effects on the output noise of practical circuits.