EFFICIENT ARITHMETIC USING SELF-TIMING

Recent advances in VLSI technology have facilitated high levels of int egration and the implementation of faster circuits on a chip, Most of the improvements in the performance of digital systems have been broug ht about by such faster technologies, However, these improvements in t echnology have brought along with them a host of other constraints, In the faster deep submicron technologies, the wire delays constitute a significant portion of the overall delay of the system and hence some of the advantages of faster technologies are lost. The high level of i ntegration necessitates clock distribution schemes which minimize skew across the die, These result in area penalties and adversely affect t he level of integration possible at the chip level, Hence, changes in the basic architecture of computing elements of a system, which when i mplemented in silicon introduces reduced interconnect delays and simpl er clock distribution networks, will. result in more effective perform ance improvements, The work presented here examines the implementation of the most basic element in any datapath-an adder, The adder, a carr y elimination adder (CEA), uses self-timing at both the algorithmic an d implementation levels and presents a minimal hardware high speed add ition mechanism, The adder exploits the nature of the input operands d ynamically, which results in its average case convergence time approac hing that of the ubiquitous carry lookahead adder (CLA) and the hardwa re complexity of a carry ripple adder (CRA). Use of self-timing result s in the elimination of a global clock and hence clock-skew. The CEA a lso possesses an interface that aids in integrating it with a system t hat is globally synchronous and facilitates static analysis for fast s ystem timing verification.