MEASUREMENT AND 2-DIMENSIONAL SIMULATION OF THIN-FILM SOI MOSFETS - INTRINSIC GATE CAPACITANCES AT ELEVATED-TEMPERATURES

Intrinsic gate-capacitance characteristics of long-channel SOI MOSFETs are investigated by measurements up to 300 degrees C and by two-dimen sional simulations up to 400 degrees C. Room temperature particulariti es related to impact ionization and floating body are successfully rep roduced by a.c. simulations. Transient simulations are used in order t o gain a deep physical insight into the observed phenomena. The contri bution of majority carriers generated by impact ionization or back acc umulation is clearly established. At high temperature, differences wit h room temperature behavior observed above and below threshold voltage are explained in terms of thermally generated excess carriers and imp act ionization reduction. The analyzed features are the threshold volt age, the subthreshold slope, and particular humps near threshold and s ubthreshold capacitance values. Implications for analog or digital cir cuit operation are briefly discussed. Copyright (C) 1996 Elsevier Scie nce Ltd