SCHEDULING WITH REGISTER CONSTRAINTS FOR DSP ARCHITECTURES

In recent years, architectural synthesis techniques for real-time sign al processing applications have been given much attention. Optimizatio n techniques have been developed which aim at minimizing the chip area for a given throughput. Especially for low to medium throughput appli cations, one can witness a growing use of embedded programmable archit ectures, referred to as ''ASIPs''. ASIPs offer programmability and com ponent re-use, which allows to reduce the time-to-market. ASIPs typica lly have an irregular parallel architecture, with distributed register structures. The data path may contain several special-purpose registe r-files, of which the number of registers is sometimes parameterizable . New retargetable code generation techniques are needed to generate h igh-quality machine code for ASIPs. During this process, a close inter action between scheduling and register allocation is essential. This p aper addresses the problem of scheduling with tight register constrain ts. A new technique for calculating the maximum number of live signals is proposed. It is based on retiming, and it is used to reduce the re gister cost of the design below a user-specified constraint. This new approach has been successfully applied to a number of real-life applic ations.