ON THE DESIGN OF A HIGH-PERFORMANCE, EXPANDABLE, SORTING ENGINE

This paper presents the design and implementation of a modular, expand able and high-performance sorter based on the rebound sorting algorith m of Chen et al. (1978). This single chip rebound sorter can sort 24, 32-bit or 64-bit, records of 2's complement or unsigned data in either ascending or descending order. The modular design of the sorter allow s direct cascading of chips for sorting more than 24 records. The mono lithic sorter is implemented in 2.0 mum CMOS technology, in a frame of 7.9 mm x 9.2 mm, which supports its 84 I/O. A pipelining scheme was u sed to achieve a sustained throughput (of cascaded sorting chips) of 1 0 MHz, while a scan-path was used to allow external control of memory elements for testing purposes. The emphasis of this paper is on the ar chitecture and circuit design of the sorter which results in a signifi cant improvement in terms of functionality, versatility and performanc e, over previously reported monolithic sorter circuits. A comparative study of other hardware sorter implementations, and sorting with a gen eral purpose processor, illustrates the performance advantages and fun ctional versatility of the sorter chip reported in this paper.