THERMAL SENSITIVITY ANALYSIS FOR THE 119 PBGA - A FRAMEWORK FOR RAPIDPROTOTYPING

Citation
S. Mulgaonker et Hm. Berg, THERMAL SENSITIVITY ANALYSIS FOR THE 119 PBGA - A FRAMEWORK FOR RAPIDPROTOTYPING, IEEE transactions on components, packaging, and manufacturing technology. Part A, 19(1), 1996, pp. 66-75
Citations number
9
Categorie Soggetti
Engineering, Eletrical & Electronic","Engineering, Manufacturing","Material Science
ISSN journal
10709886
Volume
19
Issue
1
Year of publication
1996
Pages
66 - 75
Database
ISI
SICI code
1070-9886(1996)19:1<66:TSAFT1>2.0.ZU;2-D
Abstract
New package prototyping is often a sequential process where the chip a nd system parameters are specified first, then the package design is i nitiated. A reduction in overall cycle time can be affected if the eve nts occur simultaneously. This study proposes a methodology for addres sing this issue. The method is outlined in the context of prototyping the 119 plastic ball grid array (PBGA) package thermal performance. Th e parameters influencing performance are system, device, or package ba sed. Ranges for the ''yet-to-be-fixed'' parameters are determined and factorial analyses are used to yield approximate linear models with in teractions for package performance. Once the device and system paramet ers are ''fixed,'' the linear equations are solved simultaneously with junction and board temperature constraints to yield a design options map for package layout. The prototyping sequence for the PBGA results in substrate thermal conductivity, mother board thermal conductivity, mother board load, and heat sink attachment as the set of ''variable'' parameters-with other parameters being ''fixed.'' The design options map gives the minimum substrate thermal conductivity needed to meet th e thermal performance specification for a particular set of parameters . The substrate specification is further related to physical attribute s required of the package in terms of thermal vias, thermal bumps and metal layers. These results are generically applicable to the PBGA fam ily. A 119 PBGA package enclosing a 2 W chip requires a minimum substr ate thermal conductivity of 0.03 W/cm-degrees C to meet the junction t emperature constraint for high performance workstation environments. R esults of the performance prediction are further verified by a composi te finite element simulation and experimental validation with prototyp es. The design options map can be recreated without any additional sim ulation studies in the event any change in the ''fixed'' parameters oc curs. The methodology described allows anticipation of design options in the ''dynamic'' environment of prototyping, and implementation of o ptimized package designs to meet performance under multiple customer e nvironments.