The gate-edge shape of an LDD p-MOSFET exhibits large influences upon
the hot carrier induced degradation and its performances. It is observ
ed that the gate-to-drain tunneling current is strongly correlated to
the reentrant gate oxide thickness and to the device degradation. A si
mple model is then constructed to provide an explanation for the obser
vation. Under the tunneling current measurement conditions, a thicker
oxide al the gate-edge leads to a weaker peak electric field in the p-
LDD and to a lower gate-to-drain current. On the other hand, under the
hot carrier stressing conditions, the thicker oxide decreases the oxi
de electric field and thus suppresses the hot electron injection. The
observed correlation can be employed to monitor the process induced ga
te-edge (overlap) variation.