A QUADRUPLE WELL, QUADRUPLE POLYSILICON BICMOS PROCESS FOR FAST 16 MBSRAMS

An advanced, high-performance, quadruple well, quadruple polysilicon B ICMOS technology has been developed for fast 16 Mb SRAM's. A split wor d-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 mu m(2) with conve ntional I-line lithographpy and 7.32 mu m(2) with I-line plus phase-sh ift or with deep UV lithography, The process features PELOX isolation to provide a 1.0 mu m active pitch, MOSFET transistors designed for a 0.80 mu m gate poly pitch, a double polysilicon bipolar transistor wit h aggressively scaled parasitics, and a thin-film polysilicon transist or to enhance bitcell stability, A quadruple-well structure improves s oft error rate (SER) and allows simultaneous optimization of MOSFET an d bipolar performance.