INVERTER PERFORMANCE OF 0.10 MU-M CMOS OPERATING AT ROOM-TEMPERATURE

The switching performance of 0.10 mu m CMOS devices operating at room temperature has been discussed on the basis of both experimental and s imulated results, The measured propagation delay time of a 0.10 mu m g ate length CMOS has been quantitatively divided into intrinsic and par asitic components for the first time, The results have shown that the drain junction capacitance strongly affects the propagation delay time in the present 0.10 mu m CMOS. The switching performance of a 0.10 mu m ground rule CMOS has been simulated by using device parameters extr acted from the experimental results, In the 0.10 mu m ground rule CMOS , it has been shown that an increase of the contact resistance will de grade the propagation delay time, which is one of the most essential p roblems in further device miniaturization. It has been also demonstrat ed that even if the specific contact resistance rho c is reduced to be less than 1x10(-7) Omega cm(e)(2), further reduction of the gate over lap capacitance C-ov will be required to achieve the propagation delay time to be less than 10 ps in the 0.10 mu m ground rule CMOS at room temperature.