3 LEVEL PARTITIONING ALGORITHM FOR CIRCUIT SIMULATION ON MULTIPROCESSOR

Authors
JIA XD CHEN RMM LAYFIELD AM
Citation
Xd. Jia et al., 3 LEVEL PARTITIONING ALGORITHM FOR CIRCUIT SIMULATION ON MULTIPROCESSOR, Computers & electrical engineering, 22(6), 1996, pp. 357-365
Citations number
18
Categorie Soggetti
Computer Application, Chemistry & Engineering","Computer Science Hardware & Architecture","Computer Science Interdisciplinary Applications","Engineering, Eletrical & Electronic
Journal title
Computers & electrical engineering → ACNP
ISSN journal
00457906
Volume
22
Issue
6
Year of publication
1996
Pages
357 - 365
Database
ISI
SICI code
0045-7906(1996)22:6<357:3LPAFC>2.0.ZU;2-3
Abstract
Circuit partitioning issues for circuit simulation on distributed mult iprocessors are discussed in this paper. An efficient three-level part itioning algorithm for large-scale circuit is proposed. Using this alg orithm, we can partition a large-scale circuit into r subcircuits of s imilar size while keeping the interconnect set of nodes to a minimum. This algorithm can be implemented for parallel processing. Some exampl es are given to show the performance of the algorithm. Copyright (C) 1 996 Elsevier Science Ltd