QUARTER-MICROMETER SPI (SELF-ALIGNED POCKET IMPLANTATION) MOSFETS ANDITS APPLICATION FOR LOW SUPPLY VOLTAGE OPERATION

A novel SPI (Self-aligned Pocket Implantation) technology has been pre sented, which improves short channel characteristics without increasin g junction capacitance. This technology features a localized pocket im plantation using gate electrode and TiSi2 film as self-aligned masks. An epi substrate is used to decrease the surface impurity concentratio n in the well while maintaining high latch-up immunity. The SPI and th e gate to drain overlapped structure such as LATID (Large-Angle-Tilt I mplanted Drain) technology allow use of the ultra low impurity concent ration in the channel region, resulting in higher saturation drain cur rent at the same gate over-drive compared to conventional device. The carrier velocity reaches 8 x 10(5) cm/sec and subthreshold slope is le ss than 75 mV/dec, which can be explained by low impurity concentratio n in the channel and in the substrate. The small gate depletion layer capacitance of SPI MOSFET was estimated by C-V measurement, and it can explain high performance such as small subthreshold slope. On the oth er hand, the problem and the possibility of low supply voltage operati on have been discussed, and it has been proposed that small subthresho ld slope is prerequisite for low power device operated at low supply v oltage. In addition, the drain junction capacitance of SPI is decrease d by 65% for N-MOSFET's, and 69% for P-MOSFET's both compared with con ventional devices. This technology yields an unloaded CMOS inverter of 48 psec delay time at the supply voltage of 1.5 V.