ANALYSIS OF GATE OXIDE THICKNESS HOT-CARRIER EFFECTS IN SURFACE CHANNEL P-MOSFETS

The effect of hot carrier stress on surface channel p-MOS transistors is examined for two different oxide thicknesses. It is shown that the hot carrier failure time increases by 4 orders of magnitude when the o xide thickness is reduced from 10.7 nm to 7.2 nm for stress at low gat e voltages (peak electron injection conditions), with no corresponding change in hot carrier resistance at high gate biases. Using a number of techniques, the various possible factors responsible for this are e xamined, and it is concluded that the increase in hot carrier resistan ce arises primarily due to a change in the position of hot electron in jection peak, which moves further into the drain junction region for t he thinner oxide transistors. Such effects as field-induced detrapping and the direct reduction in Delta V-t for thinner oxides are found to play secondary roles.