INTEGRATION OF 2 DIFFERENT GATE OXIDE THICKNESSES IN A 0.6-MU-M DUAL VOLTAGE MIXED-SIGNAL CMOS PROCESS

An approach for integrating 3.3 V and 5.0 V transistors with two diffe rent gate oxide thickness lavers, which eliminates the compromise betw een the transistor performance and reliability of the gate oxide layer s, is described. The approach is robust, since gate oxide layers do no t come in contact with photoresists, and relatively cost-effective in that it adds only two coarse masking steps. This approach has been dem onstrated by integrating 16.5-nm 5.0 V and 10-nm 3.3 V gate oxide laye rs in a 0.6- mu m mixed signal CMOS process, and demonstrating good 3. 3 V and 5.0 V transistor characteristics.