BIPOLAR-TRANSISTOR DEGRADATION UNDER DYNAMIC HOT-CARRIER STRESS

Hot carrier induced bipolar transistor degradation under dynamic stres s is studied. The model, Delta I-B proportional to (I (1.8)(R) t)(0.5) , established from d.c. emitter-base reverse bias stress measurements is found to be still valid under pulse stress down to 20 ns pulse widt h, where Delta I-B is drift of base current, I-r is reverse emitter-ba se current under stress and t is stress time. Although partial degrada tion recovery is observed under d.c. emitter-base forward bias, Delta I-B from alternating reverse-forward stress representative BiCMOS circ uit operation agrees with the Delta I-B model with no significant reco very effect. This is explained by a higher degradation rate after reco very of previous damage. An experimental basis of BiCMOS circuit relia bility testing simulation is thus provided.