NUMERICAL-ANALYSIS OF A TRENCH VDMOST STRUCTURE WITH NO QUASI-SATURATION

This paper presents a modification to the conventional VDMOS transisto r which considerably reduces the effect of quasi-saturation. This modi fication consists of introducing a deep trench into the structure whic h is located in the centre of each MOS cell. By extending the gate oxi de and metalization into the trench, an accumulation layer is formed d eep into the bulk of the device, which modulates the total drift regio n resistance. A two-dimensional numerical simulator is used to investi gate the electrical and thermal performance of the device through whic h it is shown that the device not only removes the quasi-saturation ef fect, but also gives lower on-resistance, and much more attractive syn chronous rectifying characteristics when compared to the conventional VDMOST structure with an equivalent geometry.