We present through the use of Petri Nets, modeling techniques for digi
tal systems realizable using FPGAs. These Petri Net models are used fo
r logic validation at the logic design phase. The technique is illustr
ated by modeling practical circuits. Further, the utility of the techn
ique with respect to timing analysis of the modeled digital systems is
considered. Copyright (C) 1997 Elsevier Science Ltd