VERIFICATION AND VALIDATION ISSUES IN MANUFACTURING MODELS

Citation
Hs. Jagdev et al., VERIFICATION AND VALIDATION ISSUES IN MANUFACTURING MODELS, Computers in industry, 25(3), 1995, pp. 331-353
Citations number
21
Categorie Soggetti
Computer Application, Chemistry & Engineering","Computer Science Interdisciplinary Applications
Journal title
ISSN journal
01663615
Volume
25
Issue
3
Year of publication
1995
Pages
331 - 353
Database
ISI
SICI code
0166-3615(1995)25:3<331:VAVIIM>2.0.ZU;2-2
Abstract
Verification and validation are two techniques employed during the dev elopment of computer programs and the modelling of systems. Each of th ese techniques has a unique scope. Both techniques are an inherent par t of the problem specification, program coding and the final implement ation of the computer software in a real-life environment. The issues of verification and validation have become all the more critical as th e scope of modern-day computer programs have evolved from data manipul ation to performing cognitive tasks. This paper discusses the verifica tion and validation issues in all three phases of software development . It introduces the basic definitions of models, verification and vali dation and goes on to describe their scope. Finally, the paper describ es the lessons learnt from the validation of a Generalised Real-Time J ob Shop Control System in a real-life manufacturing environment.