Gjm. Dormans et al., PROCESSING AND PERFORMANCE OF INTEGRATED FERROELECTRIC AND CMOS TEST STRUCTURES FOR MEMORY APPLICATIONS, Integrated ferroelectrics, 6(1-4), 1995, pp. 93-109
The feasibility of integrating ferroelectric thin films with silicon C
MOS technology was investigated by processing a ferroelectric process
evaluation module which contains ferroelectric and CMOS test structure
s and some memory cells. The smallest cells have a ferroelectric capac
itor (FECAP) of 25 mu m(2). The FECAPs were made with Pt/Ti electrodes
and with Pb(Zr,Ti)O-3 deposited by a modified sol-gel technique or by
organometallic chemical vapour deposition. The back-end processing in
cludes the insulation and interconnection of the FECAPs and the MOS tr
ansistors. The ferroelectric processing has only a slight influence on
the CMOS properties. The properties of the FECAPs improve significant
ly by an additional anneal in oxygen. Both CMOS and FECAP properties a
llow a proper functioning of the memory cells. These can be reliably o
perated at supply voltages as low as 3 V and pulse widths down to 20 n
s. The endurance of the memory cells exceeds 10(13) read/write cycles.