A STUDY OF CARRIER-TRAP GENERATION BY FOWLER-NORDHEIM TUNNELING STRESS ON POLYCRYSTALLINE-SILICON SIO2/SILICON STRUCTURES/

Deep level transient spectroscopy was used to study carrier traps indu ced in n(+)-polycrystalline-silicon/90 Angstrom-thick SiO2/p-type sili con material-system capacitors. The capacitors were fabricated using a 0.50 mu m complementary metal-oxide-silicon (CMOS) process flow. The capacitor structures were subjected to constant-voltage Fowler-Nordhei m (FN) stressing at temperatures between 50 and 300 K. It was observed that stressing at temperatures above 150 K induces a 0.20 eV-wide ban d of closely-spaced SiO2/Si interface hole-traps centered at 0.55 eV a bove the edge of the valence band in silicon. For the same stress leve l, the concentration of traps in the band decreases with decreasing te mperature, and the band is undetectable at stress temperatures below 1 50 K. FN stress at temperatures of 150 K and below is observed to indu ce defect states in the silicon substrate 600-1000 Angstrom below the interface. The silicon defects observed in this study give rise to ele ctron traps at 0.30, 0.35, and 0.37 eV below the bottom of the conduct ion band. The former two traps are suggested to arise from the configu rationally bistable boron-vacancy pair. The latter trap, which is unst able above similar to 150 K, is tentatively ascribed to the isolated v acancy. Copyright (C) 1996 Elsevier Science Ltd