The effects of the nonlinearity and polarization relaxation of storage
capacitor on DRAM R/W operations are explained using a simple model a
nd PSPICE simulation. For a given line-voltage design and pass device,
the voltage signal and the READ/WRITE times depend on the exact shape
of the Q-V curve and on the amount of polarization relaxation. It has
been found that typical high dielectric constant paraelectric materia
ls provide smaller voltage signals than the linear capacitor, and exhi
bit slower READ but faster WRITE compared to the linear capacitor.