TECHNOLOGY AND CHARACTERIZATION POLYSILICON EMITTER BIPOLAR-TRANSISTORS FOR POWER APPLICATIONS

In order to increase the current gain via a reduction of the emitter-b ase junction saturation current density J(SBE), a technological study of the fabrication of polysilicon emitter bipolar power transistors ha s been made. The wafer loading in the LPCVD furnace prior to polysilic on deposition and the substrate orientation affect the nature of the o xide formed at the polysilicon/monocrystal interface. In addition they have an effect on the emitter doping diffusion, thus modifying the me asured electrical characteristics. The importance of the crystal quali ty of the collector epitaxy has been highlighted from the dynamic char acterization and the determination of the J(SBE) values. For a blockin g voltage of 600 V, a current gain of 80 at a J(SBE) value of 1.75 x 1 0(-13) A/cm(2) has been obtained.