SUB-20 PS HIGH-SPEED ECL BIPOLAR-TRANSISTOR WITH LOW PARASITIC ARCHITECTURE

Reducing parasitic capacitance and resistance is an effective means of both improving ECL gate delay and increasing f(T) values, In this pap er, we demonstrate a device with sub-20 ps t(pd) values even at f(T) = 23 GHz, a performance which has been achieved by implementing a numbe r of techniques, These include 1) low-stress deep- and shallow-trench isolation to reduce C-CB, 2) a low-concentration collector design to r educe C-CB; 3) NiSi-salicided base and emitter electrodes to reduce R( B), and 4) a shallow base formed by double diffusion technology for re latively high f(T) with a low-concentration collector design, The low- concentration collector design gives the device a high breakdown volta ge of 6.2 V.