A HIGH-PERFORMANCE SUPER SELF-ALIGNED 3-V 5-V BICMOS TECHNOLOGY WITH EXTREMELY LOW PARASITICS FOR LOW-POWER MIXED-SIGNAL APPLICATIONS/

A high performance BICMOS technology, BEST-2 (Bipolar Enhanced super S elf-aligned Technology) designed for supporting low-power multiGHz mix ed-signal applications is presented, Process modules to produce low pa rasitic device structures will be described, The developed BiCMOS proc ess implemented with 1 mu m design rules (0.5 mu m as one nesting tole rance) has achieved f(t) and f(max) for npn bipolar (A(e) = 1x2 mu m(2 )) of 23 GHz and 24 GHz at V-ce = 3 V, respectively, with BVceo greate r than or equal to 5.5 volts, and beta V-A product of 2400. Typical me asured ECL gate delay is 48 ps/37 ps per stage(A(e) = 1 x 2 mu m(2); 5 00 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide = 125 Angstrom, L(eff) = 0.6 mu m; V-th,V-nch = 0.45 V; V- th,V-pch = - 0.45 V) 70 ps/stage, BiCMOS phase-locked-loop (emitter wi dth = 1 mu m; gate L(eff) = 0.7 mu m) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW [1].