A SYSTEMATIC LAYOUT-BASED METHOD FOR THE MODELING OF HIGH-POWER HBTS USING THE SCALING APPROACH

A systematic scaling approach for the modeling of high-power/large-siz e HBT's is presented, This approach is based on: 1) identifying and ch aracterizing the elementary cell, and 2) modeling the input/output int erconnections using the device's physical layout. The proposed approac h reduces the optimization problem for the large-size device to the ea sier fitting of the lumped equivalent circuit of the elementary cell, It is shown that there is a good agreement between the predicted resul ts, using the developed model, and the available measurements for diff erent bias points, Such a modeling approach is particularly appealing for high-power applications where the large-signal characterization of large-size devices becomes a difficult task, particularly for on-wafe r devices,