COMPARISON OF NMOS AND PMOS HOT-CARRIER EFFECTS FROM 300 TO 77 K

Since hot carrier effects can pose a potential limit to device scaling , hot-carrier-induced device degradation has been one of the major con cerns in modern device technology, Currently, there is a great interes t in pursuing low-temperature operation of MOS devices since it offers many advantages compared to room temperature operation, Also, low-tem perature operation is often required for space applications. However, low-temperature operation exacerbates hot carrier reliability of MOS d evices, Even though hot carrier effects are significantly worse at low temperature, most of the studies on hot-carrier-induced device degrad ation were done at room temperature and little has been done at low te mperature, In this work, hot-carrier-induced device degradation is cha racterized from 77 K to room temperature for both NMOS and PMOS device s with the emphasis on low-temperature behavior of hot carrier degrada tion, For NMOS devices, the worst case bias condition for hot carrier effects is found to be a function of temperature, It is also determine d that one of the primary reasons for the great reduction on hot carri er device lifetime at low temperature is that a given amount of damage simply induces a greater reduction on device performance at low tempe rature, For PMOS devices, the initial damage appears similar for both room temperature and 77 K; however, subsequent annealing indicates tha t the damage mechanism at 77 K differs markedly from that at 300 K. Ho t carrier stressing on PMOS devices at low temperature appears to indu ce hob generation and substantial interface state creation upon anneal ing unlike 300 It stressed devices, This finding may have serious reli ability implications for PMOS devices operated at cryogenic temperatur es.