DESIGN AND CHARACTERIZATION OF SUBMICRON BICMOS COMPATIBLE HIGH-VOLTAGE NMOS AND PMOS DEVICES

This paper investigates the feasibility of integrating high-voltage bl ocking capability into a state-of-the-art submicron BiCMOS process usi ng existing processing steps, High-voltage MOS devices fully compatibl e with an existing 5 V, 0.8 mu m BiCMOS process have been designed and studied through extensive two-dimensional (2-D) process and device si mulations, The device layout parameters in proposed high-voltage NMOS (HV-NMOS) and high-voltage PMOS (HV-PMOS) devices are optimized to ach ieve highest performance possible in terms of breakdown voltage and sp ecific on-resistance with the constraints of full process compatibilit y, The optimized HV-NMOS and HV-PMOS devices using minimized unit-cell pitches of 7.8 and 7.3 mu m achieved breakdown voltages of +/-29 V an d specific on-resistances of 0.9 and 11.5 m Omega . cm(2), respectivel y. Due to their full compatibility with the existing process the high- voltage MOS devices presented in this paper can be implemented without increasing manufacturing cost, The integration of the high-voltage bl ocking capability into the submicron BiCMOS process can expand its app lication field to include high-voltage input and output (I/O) function s on the same chip with high-speed analog and high-density digital sig nal processing circuitry.