SYSTEM-LEVEL HARDWARE MODULE GENERATION

In complex modern day electronic systems, far more time is spent in de signing the boards, writing the software to drive and integrate the ha rdware, and other such system level issues, than is spent in designing any application-specific IC's that may be needed. Unfortunately, most of the research in computer-aided design has been focussed on the mor e glamorous ASIC design problem, as a result of which the design metho dologies and tools at the system level are much more primitive than at the chip level. We have developed a design framework for application- specific systems, called SIERA, that addresses the higher level aspect s of system design, including multichip design issues at the boardleve l, and hardware-software codesign and integration, in addition to the design of individual ASIC's. SIERA allows rapid-prototyping of multibo ard systems where the functionality is implemented using a mix of dedi cated hardware modules and ASIC's, as well as software running on prog rammable hardware modules. A key step in the design methodology provid ed by SIERA is that of generating the physical implementation of the s ystem hardware from a description of the system architecture. The anal ogue of this problem at the chip level is referred to as silicon assem bly or silicon compilation. In this paper we address this problem at t he system level, and describe how the generation and interfacing of bo ard-level modules, board-level physical design, simulation of custom b oards, and the overall management of board design are handled in SIERA . While some of the problems could be solved by adapting or extending techniques from the existing ASIC design tools, others required new ap proaches. Case-studies of several real-life applications are also pres ented to demonstrate the effectiveness of the board-level physical des ign methodology embodied in SIERA compared to the traditional PCB desi gn systems.