CUMULATIVE BALANCE TESTING OF LOGIC-CIRCUITS

We present a new test response compression method called cumulative ba lance testing (CBT) that extends both balance testing and accumulator compression testing. CBT uses an accumulated balance signature, and it guarantees very high error coverage (over 99%) for various error mode ls. We demonstrate that the single stuck-line (SSL) fault coverage of CBT for many of the ISCAS 85 combinational benchmark circuits is 100%, and for all but one circuit, the fault coverage is over 99.5%. To mak e processor circuits self-testing, any existing accumulators and count ers can be exploited to implement CBT. Its ease of implementation, pro vably high error coverage, and exceptionally high SSL fault coverage, even with reduced (nonexhaustive) test sets, make CBT suitable for the built-in self testing of processor circuits that require a guaranteed level of test confidence.