A BUFFER DISTRIBUTION ALGORITHM FOR HIGH-PERFORMANCE CLOCK NET OPTIMIZATION

We propose a new approach for optimizing clock trees, especially for h igh-speed circuits. Our approach provides a useful guideline to a desi gner; by user-specified parameters, three of these tradeoffs will be p rovided in this paper. 1) First, to provide a ''good'' tradeoff betwee n skew and wire length, a new clock tree routing scheme is proposed. T he technique is based on a combination of hierarchical bottom-up geome tric matching and minimum rectilinear Steiner tree. Our experiments co mplement the theoretical results. 2) For high-speed clock distribution in the transmission line mode (e.g., multichip modules) where interco nnection delay dominates the clock delay, buffer congestion might exis t in a layout. Using many buffers in a small wiring area results in su bstantial interline crosstalks as well as wirability, when the elongat ion of the imbalanced subtrees is necessary. Placing buffers evenly (l ocally or globally) over the plane at the minimum impact on wire lengt h increase helps avoiding buffer congestion and results in less crosst alk between clock wires. Thus, an effective technique for buffer distr ibution will be proposed. Experimental results verifies the effectiven ess of the proposed algorithms. 3) Finally, a postprocessing step cons training on phase-delay is also proposed. The technique is based on a combination of hierarchical bottom-up geometric matching and bounded r adius minimum spanning tree. The proposed algorithm has an important a pplication in MCM clock net synthesis as well as VLSI clock net synthe sis.