A UNIFIED DESIGN METHODOLOGY FOR CMOS TAPERED BUFFERS

In this paper, the various disparate approaches to CMOS tapered buffer design are unified into an integrated design methodology. Circuit spe ed, power dissipation, physical area, and system reliability are the f our performance criteria of concern in tapered buffers, and each place s a separate, often conflicting, constraint on the design of a tapered buffer. Enhanced short-channel tapered buffer design equations are pr esented for propagation delay and power dissipation, as well as a new split-capacitor model of hot-carrier reliability of tapered buffers an d a two-component physical area model. Each performance criterion is i ndividually investigated and analyzed with respect to the number of st ages and tapering factor, and the interaction of the four criteria is examined to develop both a qualitative and a quantitative understandin g of the various design tradeoffs. The creation of process dependent l ook-up tables for optimal buffer design is described, and a methodolog y to apply these look-up tables to application-specific tapered buffer s for both unconstrained and constrained systems is developed. Summari zing, the methodology described in this paper simultaneously considers the interrelated issues of circuit speed, power dissipation, physical area, and system reliability, permitting the efficient design of tape red buffers.