M. Agarwala et Pt. Balsara, AN ARCHITECTURE FOR A DSP FIELD-PROGRAMMABLE GATE ARRAY, IEEE transactions on very large scale integration (VLSI) systems, 3(1), 1995, pp. 136-141
This paper describes an application specific architecture for field-pr
ogrammable gate arrays (FPGA's). Emphasis is placed on the logic modul
e architecture and channel segmentation for the FPGA's targeted for ap
plication areas related to digital signal processing (DSP). The propos
ed logic module architecture is well-suited for efficient implementati
on of frequently used logic functions in the DSP application area. Thi
s is mainly because it is possible to implement most of these function
s using one logic module, which results in a reduction in both the net
lengths and the number of antifuses used. The performance improvement
s are achieved by customizing the logic module architecture and the pr
ogrammable interconnect to suit the requirements of DSP applications.