Nc. Chou et Ck. Cheng, ON GENERAL ZERO-SKEW CLOCK NET CONSTRUCTION, IEEE transactions on very large scale integration (VLSI) systems, 3(1), 1995, pp. 141-146
We propose a simulated annealing based zero-skew clock net constructio
n algorithm that works in arny routing spaces, from Manhattan to Eucli
dean, with the added flexibility of optimizing either the wire length
or the propagation delay. We first devise an O(log n) tree grafting pe
rturbation function to construct a zero-skew clock tree under the Elmo
re delay model. This tree grafting scheme is able to explore the entir
e solution space asymptotically. A Gauss-Seidel iteration procedure is
then applied to optimize the Steiner point positions. Experimental re
sults have shown that our algorithm can achieve substantial delay redu
ction and encouraging wire length minimization compared to previous wo
rks.