AVPGEN - A TEST GENERATOR FOR ARCHITECTURE VERIFICATION

This paper describes a system (AVPGEN) for generating tests (called ar chitecture verification programs or AVP's) to check the conformance of processor designs to the specified architecture. To generate effectiv e tests, AVPGEN uses novel concepts like symbolic execution and constr aint solving, along with various biasing techniques, Unlike many earli er systems that make biased random choices, AVPGEN often chooses inter mediate or final values and then solves for initial values that can le ad to the desired values. A language called SIGL (symbolic instruction graph language) is provided in AVPGEN for the user to specify templat es with symbolic constraints. The combination of user-specified constr aints and the biasing functions is used to focus the tests on conditio ns that are interesting in that they are likely to activate various ki nds of bugs. The system has been used successfully to debug many S/390 processors and is an integral part of the design process for these pr ocessors.