SEQUENTIAL-CIRCUIT TESTABILITY ENHANCEMENT USING A NONSCAN APPROACH

Recent studies show that a stuck-at test applied at the operational sp eed of the circuit identifies more defective chips than a test having the same fault coverage but applied at a lower speed. Design-for-testa bility approaches based on full scan, partial scan, or silicon-based s olutions such as CrossCheck achieve very high stuck-at fault coverage. However, in all these Eases, the tests have to be applied at speeds l ower than the operation speed. Tn this work, we investigate various de sign-for-testability (DFT) techniques for sequential circuits that per mit at-speed application of tests while providing for very high fault coverage. The method involves parallel loading of hip-hops in test mod e for enhanced controllability combined with probe point insertion for enhanced observability. Fault coverage and ATG effectiveness improved to greater than 96% and 99.7%, respectively, for the ISCAS89 sequenti al benchmark circuits studied when these nonscan DPT techniques were u sed. The average area overhead for the nonscan DFT enhancements was 9. 9% for standard cell implementations of three circuits synthesized fro m high-level descriptions, compared to 20.2% for full scan. ATG effect iveness improved to greater than 99.3% for all three circuits with the nonscan DFT enhancements.