ARCHITECTURES FOR LARGE-CAPACITY CAMS

Content addressable memories (CAMs) have significantly lower capacitie s than RAMs. Following a summary of large-capacity CAM applications an d a brief tutorial look at CAM operation, this paper reviews the sourc es of this capacity disadvantage: comparator area overhead and difficu lty implementing two-dimensional decoding. Past attempts at achieving higher CAM density and capacity are reviewed, and advantages and disad vantages of each are discussed qualitatively. Architectures are divide d into the broad classes of serial and fully parallel. The former incl ude bit-serial, Orthogonal-RAM-based, insertion-memory, word-serial, m ultiport, vector-centered, pattern-addressable memory, and systolic as sociative memory. The latter include standard architectures, post-enco ding, and pre-classification. A taxonomy, providing the first structur ed comparison of existing techniques, is presented. Thereafter, four a rchitectures (two serial and two fully parallel) are quantitatively an alyzed, in terms of delay, area, and power, and the cost-performance m easures area x delay and power x delay. The fully-parallel architectur es, despite their high cost, produce superior cost-performance results .