Baa. Antao et Aj. Brodersen, BEHAVIORAL SIMULATION FOR ANALOG SYSTEM-DESIGN VERIFICATION, IEEE transactions on very large scale integration (VLSI) systems, 3(3), 1995, pp. 417-429
Synthesis of analog circuits is an emergent field, with efforts focuse
d at the cell level, With the growing trend of mixed ASIC designs that
contain significant portions of analog sections, compatible design me
thodologies in the analog domain are necessary to complement those in
the digital domain. The synthesis process requires an associated verif
ication process to ensure that the designs meet performance specificat
ions at the onset, In this paper we present a behavioral simulation me
thodology for analog system design veri,1fication and design space exp
loration, The verification task integrates with analog system-level sy
nthesis for an integrated synthesis-verification process that avoids e
xpensive post synthesis simulation by invoking external simulators. Th
us rapid redesign at the architectural level can be undertaken for des
ign parameter variation and during optimization, The verification suit
e is composed of a repertoire of analysis modes that include time and
frequency domain analysis, sensitivity analysis and distortion analysi
s. Besides verification of design specifications, these analysis modes
are also used to generate metrics for comparison of various architect
ural choices that could realize a given set of specifications. The imp
lementation is in the form of a behavioral simulator, ARCHSIM.