A layout to minimize parasitic elements which reduce the common emitte
r Heterojunction Bipolar Transistor (HBT) gain and efficiency is descr
ibed. Layout modifications are based upon consideration of the HBT dev
ice model that predicts better performance by reducing feedback elemen
ts. Reducing the base contacts size to minimize extrinsic base-collect
or capacitance, and reducing inductance in the ground connection are t
he primary paths to better performance. The improvements in small sign
al and power performance for several HBT variations are described. The
changes result in a 320 mu m(2) emitter area HBT which operating puls
ed at 10 GHz delivers 1.25 W output power with 10.5 dB associated gain
and 56% power-added efficiency.