DEEP-LEVEL TRAPPING IN ION-IMPLANTED INP JFETS

The trapping mechanisms which cause low-frequency transconductance and output resistance dispersion in ion-implanted InP JFETs are examined. The trapping activity at room temperature occurs primarily between 10 0 Hi and 1 MHz and is caused by electron traps located at the access r egion surface and in the substrate below the channel. By monitoring th e characteristic frequencies of the dispersion as a function of temper ature, the activation energies of the traps were determined. The trapp ing mechanism responsible for the low-field transconductance dispersio n appears to be a surface state with an activation energy of 0.28 eV. The output resistance dispersion indicates several traps with major on es at 0.44 and 0.55 eV at operating bias. Low-frequency noise peaks ca used by the traps were found to be consistent with the dispersion meas urements. After subtracting the trap Lorentzian contributions, the Hoo ge parameter was found to be 4 x 10(-4).