LOW-COST AND LOW-POWER SILICON NPN BIPOLAR PROCESS WITH NMOS TRANSISTORS (ADRF) FOR RF AND MICROWAVE APPLICATIONS

A silicon bipolar process for RF and microwave applications, which fea tures 25-GHz double-polysilicon self-aligned npn bipolar transistors w ith 5,5-V BVCEO, optional 0.7-mu m (L(eff)) NMOS transistors with p(+) polysilicon gates for switch applications, lateral pnp transistors, h igh and low valued resistors, p(+) polysilicon-to-n(+) plug capacitors , and inductors is described. The npn transistors utilize nitride-oxid e composite spacers formed using sacrificial TEOS spacers, a process w hich is simpler than the previously reported composite spacer processe s, Use of the composite spacer structure virtually eliminates problems relating to the extrinsic-intrinsic base link-up and reduces plasma i nduced damage associated with the conventional spacer process. Microwa ve and RF capabilities of the process up to several GHz are demonstrat ed by fabricating and characterizing RF amplifiers, low noise amplifie rs, and RF switches.