EXTRACTION OF GATE DEPENDENT SOURCE DRAIN RESISTANCE AND EFFECTIVE CHANNEL-LENGTH IN MOS DEVICES AT 77 K

A new extraction technique for obtaining the parasitic source/drain re sistance and the effective channel length of an MOS device at 77 K is presented, Unlike previous methods, both parameters are assumed to var y with the gate voltage, This results in positive and physically meani ngful results at any temperature, Simulation results show that, in non -LDD devices, the source/drain resistance decreases and the effective channel length increases with gate bias, indicating that the gate depe ndence of both parameters is inherent to MOS devices.