DYNAMIC RECONFIGURATION SCHEMES FOR MEGABIT BICMOS SRAMS AND PERFORMANCE EVALUATION

In this paper two dynamic configuration schemes are discussed for mega bit BiCMOS static random access memories (SRAMs). Dynamic reconfigurat ion schemes allows failure detection at the chip level and automatic r econfiguration to fault free memory cells within the chip. The first s cheme is a standby system approach where the I/O lines of the memory c an be dynamically switched to spare bit slices in the SRAM. This schem e is implemented through a switching network al the memory interface. Every memory access is controlled by a fault status table (FST) which memorizes the fault conditions of each memory block. This FST is imple mented outside the memory system. A second dynamic reconfiguration sch eme for BICMOS SRAMs is addressed through a graceful degradation appro ach. Basic design considerations and performance evaluation of megabit BiCMOS SRAMs using dynamic reconfiguration schemes are presented. The basic properties of the proposed schemes and a prototype VLSI chip im plementation details are discussed. BiCMOS SRAM access time improvemen t of about 35%, chip area of 25%, and chip yield of 10% are achieved, respectively, as compared to conventional methods. A comparison of rel iability improvement of 1 Mb BiCMOS SRAMs using dynamic configuration schemes is presented. These two dynamic reconfiguration schemes have c onsiderable importance in reliability improvement when compared to con ventional methods. The major advantage is that the size of reconfigura tion of the system can be considerably reduced. Copyright (C) 1997 Els evier Science Ltd.